Fault tolerance and redundancy in hardware and firmware for the Phase-II Demonstrator project in preparation for High Luminosity LHC at CERN
by
AlbaNova C4:3031
AlbaNova Main Building
Abstract:
The Large Hadron Collider at CERN is scheduled to undergo upgrades in 2026-2028 to significantly increase its luminosity. These upgrades, while providing the experiments with a higher collision rate, pose a number of challenges to the design of the hardware and software in the detectors. The Tile Calorimeter (a scintillating sampling calorimeter read out by photomultiplier tubes) at the ATLAS experiment will have its read-out electronics completely replaced to enable performance and reliability improvements.
Advances in electronics, new requirements due to the luminosity upgrade as well as lessons learned from the current readout scheme drove development with the goals to partition the readout into small independent units with full granularity readout and a robust mitigation strategy for radiation induced errors. To verify the functionality of the new system while retaining backward compatibility a “Demonstrator” has been developed to emulate the current functionality while using new and improved hardware.
The board responsible for managing digitized calorimeter data and communicating with the offdetector electronics, called the DaughterBoard, is the main focus of this thesis. It has two electrically isolated sides for redundancy where each side consists of voltage regulators, two optical transceivers, a GigaBit transceiver chip (for clocking and configuration) and a Kintex FPGA for data processing.
In addition to data management and transmission, the FPGA (and every other component) needs to be able to withstand the effects of radiation both in terms of total dose (ionization and displacement damage) and due to single event effects. The DaughterBoard was developed with this in mind and has undergone several radiation tests during its development to verify reliability and fault tolerance.
