Speaker
Description
Optical atomic clocks with $10^{-18}$ fractional frequency uncertainty enable a broad range of applications, including precise tests of fundamental physics and relativistic geodesy. In the past years, several studies have reached this level of uncertainty [1-3]. In the cited experiments, a single ion in an RF Paul trap was used for frequency stabilization. Owing to the low signal-to-noise ratio of a single atom, averaging times of several weeks are typically required to resolve $10^{-18}$ inaccuracies. Interrogating $N$ ions simultaneously reduces the required averaging time by $1/ \sqrt{N}$, as proposed in 2012 [4], and nevertheless allows high accuracy clocks with systematic uncertainties below $10^{-19}$ [5].
To store more ions on a smaller footprint, traps must be miniaturized, which can be achieved using conventional semiconductor manufacturing, yielding so-called “chip traps”. A prominent implementation is the surface trap [6,7], in which all RF and DC electrodes lie in a single plane and the ion is trapped $\sim 100~\mu\text{m}$ above the chip surface. For clock applications, however, this 2D geometry has drawbacks: The lack of point symmetry around the RF null leads to non-vanishing RF magnetic fields at the ion, and confinement is typically weaker [8] and less harmonic than in 3D geometries. It is therefore of particular interest to combine industrially mature processes with 3D electrode designs. An initial step was taken by Auchter et al. [8], who realized a 3D chip-trap structure on silicon via wafer bonding in the highly automated manufacturing environment of Infineon Technologies.
In my doctoral research, a collaboration between Infineon and the Physikalisch-Technische Bundesanstalt (PTB), this approach will be advanced by replacing silicon with glass and implementing a point-symmetric RF electrode design. Unlike silicon, glass does not generate photocharges from stray light at wavelengths typically needed for ion trap experiments, allowing to omit a continuous shielding layer, reducing RF capacitance and thus on-chip power dissipation [9]. The substrate change, however, introduces challenges because Infineon’s processes are optimized for silicon wafers, and new processes are required to integrate through-glass vias (TGVs) and through-holes for optical access. To this end, we showed the compatibility of LIDE® (Laser induced deep etching) with our trap fabrication.
A 3D trap prototype is currently in fabrication. We will characterize key performance metrics such as heating rate, stray fields and micromotion in a cryogenic setup at Infineon in Villach and in a room temperature setup at PTB’s Quantum Technology Competence Center (QTZ).
[1] C.W. Chou et al., Phys. Rev. Lett. 104, 070802 (2010).
[2] N. Huntemann et al., Phys. Rev. Lett. 116, 063001 (2016).
[3] H. N. Hausser et al., Phys. Rev. Lett. 134, 023201 (2025).
[4] N. Herschbach et al., Appl. Phys. B 107, 891–906 (2012).
[5] J. Keller et al., Phys. Rev. A 99, 013405 (2019).
[6] M. Valentini et al., Phys. Rev. X 15, 041023 (2025).
[7] Z.D. Romaszko et al., Nat Rev Phys 2, 285–299 (2020).
[8] S. Auchter et al., Quantum Sci. Technol. 7, 035015 (2022).
[9] M. Dietl et al., Adv Quantum Technol. 8, no. 11 (2025).
| Academic level | PhD student |
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