Speaker
Description
Trapped ions are a leading hardware platform for quantum computing, but scaling to a large number of qubits remains a significant challenge [1]. To overcome this, it is essential to mitigate heating effects and integrate photonic elements directly into the trap for reliable light delivery. While semiconductor substrates, such as silicon, are commonly used for surface ion trap fabrication due to established processing expertise, they pose challenges due to laser-induced charging and RF losses [2]. These issues can be addressed by using dielectric substrates like fused silica, which offer a wider bandgap, lower RF losses, and inherent optical transparency. This enables the integration of optical elements directly into the substrate, eliminating the need for additional shielding and facilitating the development of scalable ion trap architectures.
My PhD project focuses on the design and fabrication of a surface ion trap on a fused silica substrate that integrates 3D microstructures directly into the substrate. The microstructures are fabricated using a Laser Selective Etching (SLE) technique, allowing to etch out complex structures from the substrate up to micrometer precision [3]. This method enables the monolithic integration of 3D structures, such as holes for high optical access, into the ion trap chip, facilitating laser access and ion loading.
In contrast to other monolithically fabricated ion traps with SLE techniques [4, 5], the method is incorporated into a scalable fabrication process provided by the means of a large-scale semiconductor foundry. This requires the development of a suitable protection layer during the etch process that shields the structured metal electrodes on the wafer front side from the etchant.
Once the fabrication of the integrated ion trap is complete, the chip will be integrated into a cryogenic setup and evaluated in terms of trapping performance and heating rates. The built-in high optical access slot will enable more flexible single-ion addressing using a qubit laser directed from the vertical axis of the chip. Additionally, this slot can be used for integrated detection of ion fluorescence by incorporating Single Photon Avalanche Diodes (SPADs) beneath the ion trap chip, allowing for the detection of light transmitted through the slot. Ultimately, this project aims to demonstrate a scalable surface ion trap architecture that can be used as a building block for the development of practical quantum computing technologies.
[1] C. D. Bruzewicz, J. Chiaverini, R. McConnell, J. M. Sage; Trapped-ion quantum computing: Progress and challenges. Appl. Phys. Rev. 1 June 2019; 6 (2): 021314.
[2] M.Dietl, M.Valentini, F.Anmasser, et al. Test and Characterization of Multilayer Ion Traps on Fused Silica. Adv Quantum Technol.8, no. 11 (2025): e00412.
[3] J. Gottmann, et al. Selective Laser-Induced Etching of 3D Precision Quartz Glass Components for Microfluidic Applications—Up-Scaling of Complexity and Speed. Micromachines 2017, 8, 110.
[4] A. Menon, et al. Monolithic Segmented 3D Ion Trap for Quantum Technology Applications. arXiv:2603.16048 (2026)
[5] C. Peters, et al. Selective laser-induced etching (SLE) of transparent materials for microelectronic components and quantum computing applications. Proc. SPIE 12873, Laser-based Micro- and Nanoprocessing XVIII, 128730A (12 March 2024)
| Academic level | PhD student |
|---|